The present invention relates to a semiconductor device, and more particularly to a method of forming a gate pattern, which reduces etch bias.
As the degree of semiconductor integration increases, it becomes difficult to attain the critical dimensions (CDs) of a semiconductor device. Since etch bias may be locally increased during an exposure process and an etching process due to loading effects, defects may be generated such that the CD of the pattern cannot be obtained in a specific region such as a peripheral circuit region.
As the size of the transistor decreases, it may be difficult to attain a gate CD because of the loading effect in the peripheral circuit region, which causes the rapid decrease of the process margins,
In a memory device such as a DRAM, the gate of a transistor in a cell region and in the peripheral circuit region may be formed at the same time. In the peripheral circuit region, which has relatively less dense isolated gate patterns than the cell region, it is difficult to attain a gate CD because of the loading effect when patterning the gates. This may be caused by designing a much larger spacing gap between the gates in the peripheral circuit than in the cell region.
In order to reduce the loading effect, dummy patterns may be disposed around the isolated gates. When the gates in the peripheral circuit region are patterned along with dummy patterns, the pseudo pattern density of the peripheral circuit region can be made similar to the pattern density of the cell region, eliminating the loading effect. Therefore, the adoption of the dummy patterns can increase the process margins during the gate patterning by decreasing the etch bias due to the loading effect which becomes locally concentrated during the patterning of the isolated gates.
FIG. 1 is a conventional layout schematically illustrating a gate process margin in a peripheral circuit region, and FIG. 2 is a magnified view of section “A” in FIG. 1.
Referring to FIGS. 1 and 2, active regions 10 formed on a substrate are defined by device isolation regions 15. Gate patterns 20 are arranged to run across the active regions 10 in the longitudinal direction, and contact holes 40 are arranged in the active regions 10 on the left and right side of the gate patterns 20 for the connection with wirings such as bit lines.
In this case, the layouts in FIGS. 1 and 2 are layouts of active regions and gates adopted in the peripheral circuit regions of a memory device, such as, a DRAM. The gate patterns 20 in the peripheral circuit region are designed with a spacing gap wider than that between the cell gates so that the gate patterns 20 are less dense.
Around a relatively isolated first gate pattern 21 of a first active region 11 in the peripheral circuit region, there are not other gate patterns 20 which are comparable to mutually dense gate patterns 23 of second active region 13 in other cell regions. Thus, when the isolated first gate pattern 21 is exposed and developed or etched, the etch bias may be locally increased around the first gate pattern 21. For this reason, the first gate pattern 21 may be patterned such that realized CDs are remarkably smaller than designed CD. To prevent this problem, in sections where the distance between the gates 20 is designed to be large, a dummy pattern 30 which is similar to the gate patterns 20 but does not actually function as a gate is placed to decrease the etch bias. By doing so, the photolithography margin is increased. However, since the dummy pattern 30 has a shape similar to those of the second dense gate patterns 23 but does not serve as a gate, the dummy pattern 30 is not formed in the active regions 10, but preferably in the device isolation regions 15.
However, as shown in FIG. 2, in a case that a gap d1 between the active regions 10 such as the first active region 11 is very narrow, (e.g., the gap d1 is about 220 nm) it is difficult to extend the dummy patterns 30 between the active regions 10. The dummy patterns 30 can be adopted when the gap between the active regions 10 is greater than 400 nm. However, when the gap d2 between the first gate patterns 21 and the second gate patterns 23 is about 940 nm, the dummy gate patterns 30 cannot be constructed, since a sufficient gap between the active regions 10 is not available. When the dummy patterns 30 are constructed, the gap d3 between the dummy patterns 30 and the second gate patterns 23 is about 470 nm.
As such, since the first gate patterns 21 maintain the isolated status in the region where the dummy patterns 30 are not adopted, the etch bias of the first gate patterns 21 is remarkably increased during the exposure, the development, and the etching. Due to this, since there is a possibility of reduction of the photolithography margin or a pattern defect such that the line width of the first gate patterns 11 is formed narrower than a designed line width or the patterns are not formed, the uniformity of the line width of the gate patterns 20 are decreased.
Therefore, a gate pattern forming method which improves the gate process margin in the peripheral circuit region where the isolated patterns are generated and where dummy gates patterns cannot be used is desirable.